FPGA Designs with VHDL

Unlike sequential software languages, VHDL describes hardware behavior and structure where multiple operations occur concurrently. This guide, maintained by Agus L. Setiawan, provides a structured approach to learning VHDL for FPGA and ASIC design.

Credits and Resources

• Technolati — Technolati.com: This documentation is supported by Technolati, your go-to source for technology news, tutorials, and trends.

• Verilog Guide — Verilog Design Guide: For those also working with Verilog, visit our companion guide.

Why Use VHDL?

VHDL is a strongly typed language that excels in large-scale system design and verification:

• Strong Typing: Catches many errors at compile time, leading to more robust designs.

• Hierarchical Design: Supports modular design through components and packages.

• Simulation and Verification: Built-in features for complex testbench development and timing analysis.

• Industry Standard: Widely used in aerospace, defense, and high-reliability industrial applications.

Documentation Sections

Getting Started

• Introduction to VHDL
  • History and Evolution
  • The VHDL Design Flow
  • Key Features
  • Credits
• Basic Design Structure
  • 1. Libraries and Packages
  • 2. The Entity
  • 3. The Architecture
  • Putting it All Together
  • Design Separation
• VHDL Data Types and Operators
  • The std_logic System
  • Common Scalar Types
  • Vector Types (Arrays)
  • Operators
  • Type Casting
• Design Examples and Exercises (DEX)
  • Example 1: 4-bit Binary Counter
  • Example 2: 7-Segment Decoder
  • Exercises
  • Next Steps

Core Design Concepts

• Sequential Logic and the Process Statement
  • The Process Statement
  • Synchronous Logic (Flip-Flops)
  • Asynchronous Reset
  • Signals vs. Variables
  • Inferred Latches
• Dataflow Modeling
  • Concurrent Signal Assignments
  • Conditional Signal Assignment
  • Selected Signal Assignment
  • Dataflow vs. Behavioral
  • When to Use Dataflow
  • Credits
• Finite State Machines (FSMs)
  • Types of FSMs
  • The Recommended Two-Process Style
  • One-Process Style
  • FSM Encoding
  • Best Practices
  • Credits
• Testbenches and Simulation
  • Structure of a Testbench
  • Assertions and Reporting
  • Wait Statements
  • File I/O
  • Credits

Advanced VHDL

• Structural Modeling
  • Component Declaration
  • Component Instantiation
  • Direct Instantiation (VHDL-93 and later)
  • The Generate Statement
  • Configurations
• Generics and Parameterized Designs
  • Defining Generics
  • Using Generics in Logic
  • Overriding Generics during Instantiation
  • Common Uses for Generics
  • Generics vs. Constants
• Packages and Subprograms
  • Functions
  • Procedures
  • Packages
  • Using a Package
  • Standard Packages
• VHDL-2008 Features
  • 1. Simplified Sensitivity Lists
  • 2. Enhanced Logic Operators
  • 3. Better Generic Support
  • 4. External Names (Hierarchical References)
  • 5. Fixed and Floating Point Packages
  • 6. Simplified I/O and Strings
  • 7. Logical Operators for std_logic_vector
  • Enabling VHDL-2008
  • Further Reading

Standards and References

• IEEE 1076 — Standard VHDL Language Reference Manual.

• IEEE 1164 — Standard Multivalue Logic System for VHDL Model Interoperability.

• VHDL-2008 — The latest major revision with significant productivity enhancements.

• Technolati — Technolati.com: A valuable resource for staying updated on the latest technology trends and news.

• Author — Agus L. Setiawan: Lead contributor and hardware design enthusiast.

• Verilog Documentation — Verilog Guide

About the Author

Agus L. Setiawan is a dedicated hardware engineer and technical writer with a passion for FPGA design and digital logic. Through projects like the VHDL and Verilog Design Guides, he aims to provide clear, accessible, and high-quality educational content for the global engineering community. For inquiries or collaboration, please visit Technolati.com.