FPGA designs with VHDL

Contents:

• 1. First project
  • 1.1. Introduction
  • 1.2. Creating the project
  • 1.3. Digital design using ‘block schematics’
  • 1.4. Manual pin assignment and compilation
  • 1.5. Load the design on FPGA
  • 1.6. Digital design using ‘VHDL codes’
  • 1.7. Pin assignments using ‘.csv’ file
  • 1.8. Converting the VHDL design to symbol
  • 1.9. Convert Block schematic to ‘VHDL code’ and ‘Symbol’
  • 1.10. Conclusion
• 2. Overview
  • 2.1. Introduction
  • 2.2. Entity and Architecture
    • 2.2.1. Entity declaration
    • 2.2.2. Architecture body
  • 2.3. Modeling styles
    • 2.3.1. Dataflow modeling
    • 2.3.2. Structural modeling
    • 2.3.3. Behavioral modeling
    • 2.3.4. Mixed modeling
  • 2.4. Packages
  • 2.5. Conclusion
• 3. Data types
  • 3.1. Introduction
  • 3.2. Lexical rules
  • 3.3. Library and packages
    • 3.3.1. ‘std_logic_1164’ package
    • 3.3.2. ‘numeric_std’ package
    • 3.3.3. ‘textio’ and ‘std_logic_textio’ packages
    • 3.3.4. Other standard packages
  • 3.4. Entity and architecture
    • 3.4.1. Entity declaration
    • 3.4.2. Architecture body
  • 3.5. Keyword ‘others’, ‘downto’ and ‘to’
  • 3.6. Data objects
  • 3.7. Data types
    • 3.7.1. Standard data type
    • 3.7.2. User-defined scalar types
    • 3.7.3. User-defined composite types
    • 3.7.4. File Type
  • 3.8. Tristate buffer
  • 3.9. Operators
    • 3.9.1. Arithmetic operators
    • 3.9.2. Logical or Boolean operators
    • 3.9.3. Relational operators
    • 3.9.4. Concatenation operators
    • 3.9.5. Assignment operator
    • 3.9.6. Shift operators
  • 3.10. Type conversion
  • 3.11. Constant and Generics
    • 3.11.1. Constants
    • 3.11.2. Generics
  • 3.12. Attributes
  • 3.13. Conclusion
• 4. Dataflow modeling
  • 4.1. Introduction
  • 4.2. Combinational circuit and sequential circuit
  • 4.3. Concurrent statements and sequential statements
  • 4.4. Delay in signal assignments
    • 4.4.1. Delta delay
    • 4.4.2. Delay with ‘after’ statement
  • 4.5. Concurrent signal assignments
    • 4.5.1. Conditional signal assignment
    • 4.5.2. Selected signal assignment
  • 4.6. Generate statement and problem with Loops
  • 4.7. Conclusion
• 5. Behavioral modeling
  • 5.1. Introduction
  • 5.2. Process block
  • 5.3. If-else statement
  • 5.4. Case statement
  • 5.5. Wait statement
  • 5.6. Problem with Loops
  • 5.7. Loop using ‘if’ statement
  • 5.8. Unintentional memories in combinational designs
  • 5.9. Code-size vs design-size
  • 5.10. Conclusion
• 6. Procedures, functions and packages
  • 6.1. Introduction
  • 6.2. Procedure
  • 6.3. Function
  • 6.4. Packages
  • 6.5. Conclusion
• 7. Verilog designs in VHDL
  • 7.1. Introduction
  • 7.2. Verilog designs in VHDL
  • 7.3. Simulation of mixed designs
  • 7.4. Conclusion
• 8. Visual verifications of designs
  • 8.1. Introduction
  • 8.2. Flip flops
    • 8.2.1. D flip flop
    • 8.2.2. D flip flop with Enable port
  • 8.3. Counters
    • 8.3.1. Binary counter
    • 8.3.2. Mod-m counter
  • 8.4. Clock ticks
  • 8.5. Seven segment display
    • 8.5.1. Implementation
    • 8.5.2. Test design for 7 segment display
  • 8.6. Visual verification of Mod-m counter
  • 8.7. Conclusion
• 9. Finite state machines
  • 9.1. Introduction
  • 9.2. Comparison: Mealy and Moore designs
  • 9.3. Example: Rising edge detector
    • 9.3.1. State diagrams: Mealy and Moore design
    • 9.3.2. Implementation
    • 9.3.3. Outputs comparison
    • 9.3.4. Visual verification
  • 9.4. Glitches
    • 9.4.1. Combinational design in asynchronous circuit
    • 9.4.2. Unfixable Glitch
    • 9.4.3. Combinational design in synchronous circuit
  • 9.5. Moore architecture and VHDL templates
    • 9.5.1. Regular machine
    • 9.5.2. Timed machine
    • 9.5.3. Recursive machine
  • 9.6. Mealy architecture and VHDL templates
    • 9.6.1. Regular machine
    • 9.6.2. Timed machine
    • 9.6.3. Recursive machine
  • 9.7. Examples
    • 9.7.1. Regular Machine : Glitch-free Mealy and Moore design
    • 9.7.2. Timed machine : programmable square wave
    • 9.7.3. Recursive Machine : Mod-m counter
  • 9.8. When to use FSM design
  • 9.9. Conclusion
• 10. Testbenches
  • 10.1. Introduction
  • 10.2. Testbench for combinational circuits
    • 10.2.1. Half adder
    • 10.2.2. Simple testbench
    • 10.2.3. Testbench with process statement
    • 10.2.4. Testbench with look-up table
    • 10.2.5. Read data from file
    • 10.2.6. Write data to file
    • 10.2.7. Half adder testing using CSV file
  • 10.3. Testbench for sequential circuits
    • 10.3.1. Simulation with infinite duration
    • 10.3.2. Simulation for finite duration and save data
  • 10.4. Conclusion
• 11. Design examples
  • 11.1. Introduction
  • 11.2. Random number generator
    • 11.2.1. Linear feedback shift register (LFSR)
    • 11.2.2. Visual test
  • 11.3. Shift register
    • 11.3.1. Bidirectional shift register
    • 11.3.2. Visual test
    • 11.3.3. Parallel to serial converter
    • 11.3.4. Serial to parallel converter
    • 11.3.5. Top level connection between serial and parallel converters
    • 11.3.6. Visual test for serial and parallel converters
  • 11.4. Random access memory (RAM)
    • 11.4.1. Single port RAM
    • 11.4.2. Visual test : single port RAM
    • 11.4.3. Dual port RAM
    • 11.4.4. Visual test : dual port RAM
  • 11.5. Read only memory (ROM)
    • 11.5.1. ROM implementation using RAM (block ROM)
    • 11.5.2. ROM implementation logic cells (distributed ROM)
    • 11.5.3. Distributed ROM vs Block ROM
    • 11.5.4. Visual test
    • 11.5.5. Defining ROM contents in file
  • 11.6. LCD interface
    • 11.6.1. Example 1
    • 11.6.2. Example 2
    • 11.6.3. Example 3 : Error counting
  • 11.7. VGA interface
    • 11.7.1. Synchronization circuit
    • 11.7.2. Visual test : change screen color with switches
    • 11.7.3. Visual test : display different colors on screen
• 12. Simulate and implement SoPC design
  • 12.1. Introduction
  • 12.2. Creating Quartus project
  • 12.3. Create custom peripherals
  • 12.4. Create and Generate SoPC using Qsys
  • 12.5. Create Nios system
  • 12.6. Add and Modify BSP
    • 12.6.1. Add BSP
    • 12.6.2. Modify BSP (required for using onchip memory)
  • 12.7. Create application using C/C++
  • 12.8. Simulate the Nios application
  • 12.9. Adding the top level VHDL design
  • 12.10. Load the Quartus design (i.e. .sof/.pof file)
  • 12.11. Load the Nios design (i.e. ‘.elf’ file)
  • 12.12. Saving NIOS-console’s data to file
  • 12.13. Conclusion
• 13. Reading data from peripherals
  • 13.1. Introduction
  • 13.2. Modify Qsys file
  • 13.3. Modify top level design in Quartus
  • 13.4. Modify Nios project
    • 13.4.1. Adding Nios project to workspace
  • 13.5. Add ‘C’ file for reading switches
  • 13.6. Simulation and Implementation
  • 13.7. Conclusion
• 14. UART, SDRAM and Python
  • 14.1. Introduction
  • 14.2. UART interface
  • 14.3. NIOS design
  • 14.4. Communication through UART
  • 14.5. SDRAM Interface
    • 14.5.1. Modify QSys
    • 14.5.2. Modify Top level Quartus design
    • 14.5.3. Updating NIOS design
  • 14.6. Live plotting the data
  • 14.7. Conclusion
• 15. Script execution in Quartus and Modelsim
  • 15.1. Quartus
    • 15.1.1. Generating the RTL view
    • 15.1.2. Loading design on FPGA board
  • 15.2. Modelsim
• 16. How to implement NIOS-designs
  • 16.1. Create project
  • 16.2. Add all files from VHDLCodes folder
  • 16.3. Generate and Add QSys system
  • 16.4. Nios system